Silicon DFT Engineer

Here’s what you need:

• A minimum of two years of experience with Hardware Design-For-Test (DFT) engineering including

• A minimum of two years of experience in silicon design and/or verification

• Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)

Bonus points if:

• Developing DFT specifications

• Industry standard DFT and design tools

• Debugging ATPG/MBIST patterns

• STA constraints and their interaction with DFT

• Experience with Root Cause Analysis

• IP / Top Scan insertion (all EDA solutions)

• IP / Top Mbist insertion (all EDA solutions)

• Scripting languages TCL/Perl/Python

• Experience with Synopsys DFT tools (Tetramax, DFT compiler, BSD compiler, Formality, Spyglass)

• Experience with JTAG and IEEE standards 1149.1 and 1149.6.

Compensation at Accenture varies depending on a wide array of factors, which may include but are not limited to the specific office location, role, skill set, and level of experience. As required by local law, Accenture provides a reasonable range of compensation for roles that may be hired in  California, Colorado, New York or Washington as set forth below.

We accept applications on an on-going basis and there is no fixed deadline to apply.

Information on benefits is here.

Role Location                              Annual Salary Range

California                                      $63,200 to $220,400

Colorado                                       $63,200 to $190,400

New York                                       $58,500 to $220,400

Washington                                  $67,300 to $202,700

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