As part of Accenture’s Industry X, the Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands on experience in architecture, logic design, verification, physical design, emulation and firmware . We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
Whether at our Silicon Design Center in Phoenix or at one of our other locations you will get to collaborate and innovate with the world’s leading product development companies. In our dynamic fast-paced environment you will get to make the impossible possible.
Accenture is invested in our team member’s growth and provide many opportunities for training and skills expansion.
Develop own physical design implementation of multi hierarchy low power designs including physical aware logic synthesis, design for testability, floor plan, place route, static timing analysis, IR Drop, EM, physical verification in advanced technology node
Resolve design flow issues related to physical design, identify potential solutions, drive execution
Deliver physical design of an end to end IP or integration of ASIC SoC design
Minimum of 1 - 3 years of experience in any of the following:
RTL2GDSIIon advanced technology nodes (7nm and below)
Bachelor’s Degree or equivalent work experience (12 years) or an Associate’s Degree with 6 years of work experience.
Experience running physical aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts, defining timing constraints exceptions, corners voltage definitions
Experience with custom or regular clock tree synthesis implementation at block level or top level, clock power reduction techniques
Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States and with Accenture.
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