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Silicon Formal Verification Engineer
Ontario - Ottawa
Job No. r00153179
Full-time
Job Description
We Are:
The Silicon Design group is a diverse team of world class silicon design, verification and validation experts. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture Consultants are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
You Are:
An experienced Formal Verification Engineer able to provide formal verification services for multiple blocks and IP’s.
The Work:
- Developing formal verification test plan
- Drive automation of formal testbenches and ensure they are a part of regressions
- Develop assertions, cover properties and connectivity checks and debug any failures in RTL regressions
- Work with cross functional teams (DV/Arch/Design/FW)
- Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
- Work as a team to grow together.
- Mentor and coach junior team members
Qualifications
Here’s what you need:
- A minimum of three years of experience with Formal Verification
- Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate Degree with 6 years of work experience).
Priority Skills
- Experience working with one or more formal verification tools such as Jasper gold, VC-Formal, Incisive Formal Verifier (IFV), Questa Formal, etc.
- Experience in interpreting design specifications and using temporal logic assertion-based languages such as SVA
- Experience in formal property verification (FPV), Sequential Logic Equivalence Checking (SEC/SEQ/SLEC), and/or academic formal methods
- Experience with hardware description languages (SystemVerilog, Verilog, VHDL) and simulators (VCS, NC, Questa).
Bonus Points If:
- Proficiency in programing/scripting languages
- In-depth knowledge of digital logic design, chip architecture and microarchitecture
- Problem solving and debug skills for complex logic and digital designs
- Team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design
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