Functional Verification Engineer

Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : Design Verification Testing
Good to have skills : NA
Minimum 7.5 year(s) of experience is required
Educational Qualification : 15 years full time education

Summary:
As a Functional Verification Engineer, a typical day involves developing and implementing comprehensive test environments to ensure the accuracy and reliability of digital designs. This role requires close collaboration with various teams to identify potential edge cases and verify that all functional aspects of the design are thoroughly tested. The engineer focuses on creating diverse testing scenarios and analyzing results to guarantee the design meets all specifications before final production stages. Continuous communication and coordination with design and architecture teams are essential to maintain alignment and address any issues promptly throughout the verification process.

Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to improve verification methodologies and processes to enhance efficiency and coverage.
- Mentor junior team members to support their professional growth and skill development.
- Coordinate cross-functional reviews to ensure alignment on verification goals and deliverables.

Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design Verification Testing.
- Strong knowledge of verification methodologies including constrained-random testing, directed testing, and coverage-driven verification.
- Experience with hardware description and verification languages such as SystemVerilog and Universal Verification Methodology.
- Ability to develop and maintain complex testbenches for block and system level verification.
- Familiarity with debugging tools and simulation environments to analyze and resolve functional issues.
- Skilled in collaborating with design and architecture teams to identify and cover corner cases effectively.

Additional Information:
- The candidate should have minimum 7.5 years of experience in Design Verification Testing.
- This position is based at our Bengaluru office.
- A 15 years full time education is required.