Design-For-Test (DFT) Engineer
Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.
Must have skills : Design for Testability (DFT)
Good to have skills : NA
Minimum 7.5 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Design-For-Test Engineer, your day revolves around ensuring that semiconductor chips are designed with features that facilitate thorough and efficient testing after manufacturing. You will work closely with various teams to embed testability elements into the design, enabling early detection of defects and improving overall product quality. Your role involves continuous collaboration and problem-solving to optimize test coverage and fault isolation, contributing significantly to the reliability and performance of silicon products. This position requires a proactive approach to integrating test strategies seamlessly within the design process to support manufacturing and quality assurance goals.
Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to identify and implement improvements in test methodologies to enhance product quality and test efficiency.
- Facilitate knowledge sharing and mentoring within the team to build expertise in design-for-test techniques.
- Coordinate cross-functional activities to ensure alignment of test strategies with overall project objectives.
Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design for Testability (DFT).
- Strong understanding of scan chain insertion and optimization techniques.
- Experience with Built-In Self-Test (BIST) architectures and implementation.
- Familiarity with boundary scan standards and their application in silicon testing.
- Ability to collaborate effectively with design and verification teams to enhance test coverage and fault isolation.
- Skilled in analyzing test data to identify defects and improve test strategies.
Additional Information:
- The candidate should have minimum 7.5 years of experience in Design for Testability (DFT).
- This position is based at our Hyderabad office.
- A 15 years full time education is required.
Hyderabad
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