Design-For-Test (DFT) Engineer
Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.
Must have skills : Design for Testability (DFT)
Good to have skills : NA
Minimum 7.5 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Design-For-Test Engineer, your day revolves around enhancing the testability of semiconductor chips by embedding specialized features during the design process. You will work closely with various teams to ensure that the chip design supports thorough testing after manufacturing, enabling early detection of defects. Your role involves continuous collaboration to refine test strategies, improve fault isolation, and contribute to delivering high-quality silicon products. This position requires a proactive approach to problem-solving and coordination across multiple disciplines to achieve optimal test coverage and efficiency.
Roles & Responsibilities:
- Expected to be an SME, collaborate and manage the team to perform.
- Responsible for team decisions.
- Engage with multiple teams and contribute on key decisions.
- Provide solutions to problems for their immediate team and across multiple teams.
- Lead efforts to integrate testability features into chip designs to facilitate effective post-manufacturing testing.
- Coordinate with design and verification teams to optimize test strategies and improve fault detection capabilities.
- Mentor junior team members by sharing knowledge and guiding their development in design-for-test methodologies.
- Drive continuous improvement initiatives to enhance test coverage and reduce time-to-market for silicon products.
Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design for Testability (DFT).
- Strong understanding of scan chain insertion and optimization techniques.
- Experience with Built-In Self-Test (BIST) architectures and implementation.
- Knowledge of boundary scan standards and their application in chip testing.
- Ability to collaborate effectively with design and verification teams to enhance test coverage.
- Familiarity with fault isolation methods and test pattern generation.
Additional Information:
- The candidate should have minimum 8 years of experience in Design for Testability (DFT).
- This position is based at our BDC6F - SEZ office.
- A 15 years full time education is required.
Bengaluru
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