The Silicon Design group is a diverse team of world class silicon engineers. We have 100+ years of cumulative hands-on experience in architecture, logic design, verification, physical design, emulation and firmware. We use the latest silicon technologies and processes to help our clients create well-designed solutions to highly complex challenges. We are designing and developing next-generation, high performance SoCs, supporting our clients in their drive to deliver their product vision to their users. We are involved in all aspects of chip design from definition and architecture through to verification and signoff. Accenture engineers are true “Silicon to SW” Partners, allowing a new breed of companies in the semiconductor ecosystem to innovate in an unparalleled time to market.
An experienced RTL Design Engineer
Contribute to the development of efficient µArchitectures and contribute to ASIC Architecture, design and verification
Understand our in-house IPs needed and how they need to be integrated, connected and verified
Drive the top-level µArchitecture definition and develop the necessary RTL
Drive the chip-level integration, verification plan development and verification
Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
Support the test program development, chip validation and chip life until production maturity
Work with FPGA engineers to perform early prototyping
Support hand-off and integration of blocks into larger SOC environments
Assist with Algorithm analysis, verification and improvement
Contribute to ASIC digital architecture, design and verification
Here’s what you need:
A minimum of five years of experience as a Digital Design Engineer and/or a Chip Lead
A minimum of five years of experience in uP and/or GPU and/or Video Processing
Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
Bonus points if:
Experience in RTL coding, synthesis and/or SoC Integration
Experience in digital design µArchitecture
System Verilog OVM/UVM experience
Python (or similar) scripting experience
Experience in SoC integration and ASIC architecture
Experience in DFT/Testability requirement and test program definition
As required by the Colorado Equal Pay Transparency Act, Accenture provides a reasonable range of minimum compensation for roles that may be hired in Colorado. Actual compensation is influenced by a wide array of factors including but not limited to skill set, level of experience, and specific office location. For the state of Colorado only, the range of starting pay for this role is $97,632-$182,600 and information on benefits offered is here.
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