- Contribute to the development of efficient µArchitectures and contribute to ASIC Architecture, design and verification
- Understand our in-house IPs needed and how they need to be integrated, connected and verified
- Drive the top-level µArchitecture definition and develop the necessary RTL
- Drive the chip-level integration, verification plan development and verification
- Supervise the RTL-to-GDS flow and assist with synthesis and timing closure
- Support the test program development, chip validation and chip life until production maturity
- Work with FPGA engineers to perform early prototyping
- Support hand-off and integration of blocks into larger SOC environments
- Assist with Algorithm analysis, verification and improvement
- Contribute to ASIC digital architecture, design and verification
- Bachelor’s Degree or Master's Degree in Electrical Engineering, Computer Science or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
- 1 year of experience in RTL coding, synthesis and/or SoC Integration
- Experience as a Digital Design Engineer or Chip Lead
- Knowledge in uP and/or GPU and/or Video Processing
- Experience in RTL coding, synthesis and/or SoC Integration
- Experience in digital design µArchitecture
- System Verilog OVM/UVM experience
- Python (or similar) scripting experience
- Experience in SoC integration and ASIC architecture
- Experience in DFT/Testability requirement and test program definition
- Experience using High Speed interfaces like PCIe, USB, MIPI
LocationsCA - San Francisco,CA - San Jose
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